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february 2010 doc id 9800 rev 4 1/19 1 tda7565 quad power amplifier with integrated step-up converter features multipower bcd technology dmos power output non-switching high efficiency amplifier switching high efficiency voltage converter high output power capability: ? 4 x 41 w max @ v s = 14.4 v ? 4 x 59 w @ v s = 14.4 v and pwm = 17.5 v full i 2 c bus driving: ? standby ? independent front/rear soft play/mute ? selectable gain 26 db - 12 db (for low noise line output function) ? high efficiency enable/disable ? voltage converter enable/disable ? regulated voltage selection ? switching frequency selection hardware mute function full fault protection dc offset detection four independent short circuit protection clipping detector with selectable threshold (1 % / 10 %) via i 2 c bus description the tda7565 is a new bcd technology quad bridge type of car radio amplifier in flexiwatt27 package specially intended for car radio applications. thanks to the dmos output stage the tda7565 has a very low distortion allowing a clear powerful sound. the built-in voltage converter control block assures a very high output power with an extremely low number of added components. furthermore, the converter makes the tda7565 compliant to the most re cent oem specifications for low voltage operation (so called 'start-stop' battery profile during engine stop), helping car manufacturers to reduce the overall emissions and thus contributing to environment protection. flexiwatt27 table 1. device summary order code package packing tda7565 flexiwatt27 tube www.st.com
contents tda7565 2/19 doc id 9800 rev 4 contents 1 block and pin connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3i 2 c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 examples of bytes sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 low voltage "start-stop" operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
tda7565 list of tables doc id 9800 rev 4 3/19 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 5. chip address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. ib1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. ib2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. db1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. db2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 10. db3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 11. db4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
list of figures tda7565 4/19 doc id 9800 rev 4 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. demoboard schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. data validity on the i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. timing diagram on the i2c bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. acknowledge on the i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. worst case condition for a start-stop system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. flexiwatt27 (vertical) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . 17
tda7565 block and pin connection diagrams doc id 9800 rev 4 5/19 1 block and pin connection diagrams figure 1. block diagram figure 2. pin connection (top view) i2c bus voltage converter control clip detector f r f svr rf rr lf lr tab s_gnd ac_gnd r in rf in rr in lf in lr out lr- pw_gnd out lr+ out lf- out lf+ out rr- out rr+ out rf- out rf+ mute1 mute2 voltage converter external circuit short circuit protection 12/26db 12/26db 12/26db 12/26db short circuit protection short circuit protection short circuit protection v cc1 v cc2 data cc gnd v s clk mg mute d00au1232a d00au1233 a tab mg pw_gnd lr out lr- cc gnd out lr+ v cc1 out lf- pw_gnd lf out lf+ svr in lf in lr s_gnd in rr in rf ac_gnd out rf+ pw_gnd rf out rf- v cc2 ck out rr- out rr+ pw_gnd rr data mute 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 25 26 22 21 23 24 27
electrical specification tda7565 6/19 doc id 9800 rev 4 2 electrical specification 2.1 absolute maximum ratings 2.2 thermal data 2.3 electrical characteristics refer to the test circuit, v s = 14.4 v; r l = 4 ; f = 1 khz; voltage converter disabled (vc off ); t amb = 25 c; unless otherwise specified. table 2. absolute maximum ratings symbol parameter value unit v opc off operating supply voltage, converter off 18 v v opc on operating supply voltage, converter on 25 v v s dc supply voltage 28 v v peak peak supply voltage (for t = 50 ms) 50 v v ck ck pin voltage 6 v v data data pin voltage 6 v i o output peak current (not repetitive t = 100 s) 8 a i o output peak current (repetitive f > 10 hz) 6 a p tot power dissipation t case = 70 c 80 w t stg , t j storage and junction temperature -55 to 150 c table 3. thermal data symbol description value unit r th j-case thermal resistance junction to case max. 1 c/w table 4. electrical characteristics symbol parameter test condition min. typ. max. unit power amplifier v s supply voltage range - 8 - 18 v i d total quiescent drain current - - 250 300 ma i d total quiescent drain current (vc on ) --350-ma p o output power (vc off ) v = 14.4 v max power (1) -41-w thd = 10 % thd = 1 % 22 18 27 22 - w w
tda7565 electrical specification doc id 9800 rev 4 7/19 p o output power (vc on ) v = 14.4v, pwm = 17.5v max power (1) -59-w thd = 10 % thd = 1 % 32 25 39 31 - w w thd total harmonic distortion p o = 1 w to 12 w; stdmode he mode; p o = 1-2 w he mode; p o = 4-12 w - 0.03 0.03 0.1 0.1 % % % p o = 1-12 w, f = 10 khz - 0.15 0.5 % c t cross talk f = 1 khz to 10 khz, r g = 600 50 55 - db r in input impedance - 60 100 130 k g v1 voltage gain 1 - 25.5 26 26.5 db g v1 voltage gain match 1 - -1 - 1 db g v2 voltage gain 2 - 11.5 12 12.5 db g v2 voltage gain match 2 - -1 - 1 db e in1 output noise voltage 1 r g = 600 ; g v = 26 db filter 20 hz to 22 khz -6070 v e in2 output noise voltage 2 r g = 600 ; g v = 26 db filter 20 hz to 12 khz -1525 v svr supply voltage rejection f = 100 hz to 10 khz; v r = 1v pk; r g = 600 50 60 - db bw power bandwidth (-3 db) 75 - - khz a sb standby attenuation - 70 100 db i sb standby current - - - 50 a a m mute attenuation - 70 90 db v os offset voltage mute and play -100 - 100 mv v am min. supply voltage threshold - 6.5 7 7.5 v slew rate - 1.5 - - v/ s t on turn on delay d2/d1 (ib1) 0 to 1 - 10 40 ms t off turn off delay d2/d1 (ib1) 1 to 0 - 10 40 ms - thermal foldback junction temperature - 155 170 185 c cd thd clip det thd. level d0 (ib1) = 0 0 1 2 % d0 (ib1) = 1 5 10 15 % v o offset detection power amplifier = play ac input = 0 1.5 2 2.5 v t hw thermal warning - - 165 - c table 4. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
electrical specification tda7565 8/19 doc id 9800 rev 4 i 2 c bus interface f scl clock frequency - - - 400 khz v il input low voltage - - - 1.5 v v ih input high voltage - 2.3 - - v v min(pin27) mute in threshold voltage amp. mute - - 1.5 v v mout(pin27) mute out threshold voltage - 3.5 - - v a m(pin 27) mute attenuation - 80 90 - - voltage converter v cc1 , v cc2 converter output voltage (vc = on) v s = 14 v d3 (ib2) = 0; d6 (ib2) = 0 d3 (ib2) = 1; d6 (ib2) = 0 d3 (ib2) = 0; d6 (ib2) = 1 d3 (ib2) = 1; d6 (ib2) = 1 - 15 16.5 17.5 18.5 -v f s voltage converter switching frequency d6 (ib1) = 0; d7 (ib1) = 0 d6 (ib1) = 1; d7 (ib1) = 0 d6 (ib1) = 0; d7 (ib1) = 1 d6 (ib1) = 1; d7 (ib1) = 1 90 135 230 360 - 120 175 300 470 khz v mgl mos gate output low voltage i o = 200 ma - 1 2 v v mgh mos gate output high voltage i o = 20 ma - 11 - v i o = 200 ma - 9.5 - v v mgclamp mos gate output clamp voltage i o = 5 ma - 11.5 - v t f fall time c o = 1 nf - 20 - ns t r rise time c o = 1 nf - 50 - ns v mgl (vc off ) mos gate output voltage with voltage converter disabled i o = 5 ma - - 0.5 v 1. saturated square wave output. table 4. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit
tda7565 electrical specification doc id 9800 rev 4 9/19 figure 3. demoboard schematic c13 10 f 21 5 18 20 22 24 10 8 6 4 14 1 7 26 23 2 16 15 12 13 11 17 c1 220nf in rf in rr in lf in lr mute out lr- out lr+ out lf- out lf+ out rr- out rr+ out rf- out rf+ r3 10 r4 3.3 1w c2 220nf c3 220nf c4 220nf 27 c6 10 f c5 1 f v cc d1 stps30l40ct sda scl dgnd v s (vbatt) c11 3300 f c7 2200 f c12 100nf c8 220nf c9 10nf stp60ne06 q1 r5 10 1w r1 50 c10 2.2nf 25 19 3 9 d00au1224b l1 100 h tda7565
i 2 c bus interface tda7565 10/19 doc id 9800 rev 4 3 i 2 c bus interface data transmission from microprocessor to the tda7565 and vice versa takes place through the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected). 3.1 data validity as shown by figure 4 , the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 3.2 start and stop conditions as shown by figure 5 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high tr ansition of the sda line while scl is high. 3.3 byte format every byte transferred to the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 3.4 acknowledge the transmitter* puts a resistive high level on the sda line during the acknowledge clock pulse (see figure 6 ). the receiver** the acknowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. * transmitter ?master ( p) when it writes an address to the tda7565 ? slave (tda7565) when the p reads a data byte from tda7565 ** receiver ? slave (tda7565) when the p writes an address to the tda7565 ? master (p) when it reads a data byte from tda7565 figure 4. data validity on the i 2 c bus sda scl data line stable, data valid change data allowed d99au1031
tda7565 i 2 c bus interface doc id 9800 rev 4 11/19 figure 5. timing diagram on the i 2 c bus figure 6. acknowledge on the i 2 c bus scl sda start i 2 cbus stop d99au1032 scl 1 msb 23789 sda start acknowledgment from receiver d99au1033
software specifications tda7565 12/19 doc id 9800 rev 4 4 software specifications all the functions of the tda7565 are activated by i 2 c interface. the bit 0 of the "address byte" defines if the next bytes are write in struction (from p to tda7565) or read instruction (from tda7565 to p). if r/w = 0, the p sends 2 "instruction bytes": ib1 and ib2. table 5. chip address bit instruction d7 address bit d6 address bit d5 address bit d4 address bit d3 address bit d2 address bit d1 address bit d0(r/w) read/write bit 0 = write instruction 1 = read instruction table 6. ib1 bit instruction d7 sel. freq. switch 1 d6 sel. freq. switch 2 d5 offset detection start (d5 = 1) offset detection stop (d5 = 0) (off) d4 front channel gain = 26db (d4 = 0) gain = 12db (d4 = 1) d3 rear channel gain = 26db (d3 = 0) gain = 12db (d3 = 1) d2 mute front channels (d2 = 0) unmute front channels (d2 = 1) d1 mute rear channels (d1 = 0) unmute rear channels (d1 = 1) d0 cd 1% (d0 = 0) cd 10% (d0 = 1)
tda7565 software specifications doc id 9800 rev 4 13/19 table 7. ib2 bit instruction d7 voltage converter enabled (d7 = 1) voltage converter disabled (d7 = 0) d6 regulated voltage selection 1 d5 test speed d4 stand-by on - amplifier not working - (d4 = 0) stand-by off - amplifier working - (d4 = 1) d3 regulated voltage selection 0) d2 to be forced to ?level 1? d1 right channel power amplifier working in standard mode (d1 = 0) power amplifier working in hi eff. mode(d1 = 1) d0 left channel power amplifier working in standard mode (d0 = 0) power amplifier working in hi eff. mode(d0 = 1) table 8. db1 bit instruction d7 thermal warning d6 x d5 x d4 x d3 x d2 offset (lf) d1 short circuit protection (ch1) d0 x table 9. db2 bit instruction d7 off status d6 x d5 clip detector output d4 x d3 x d2 offset (lr) d1 short circuit protection (ch2) d0 x
software specifications tda7565 14/19 doc id 9800 rev 4 table 10. db3 bit instruction d7 standby status d6 x d5 x d4 x d3 x d2 offset (rf) d1 short circuit protection (ch3) d0 x table 11. db4 bit instruction d7 x d6 x d5 x d4 x d3 x d2 offset (rr) d1 short circuit protection (ch4) d0 x
tda7565 examples of bytes sequence doc id 9800 rev 4 15/19 5 examples of bytes sequence 1 - turn-on of the power amplifier with 26 db gain, mute on, diagnostic defeat, high eff. mode, voltage converter disabled. 2 - turn-off of the power amplifier 4 - offset detection procedure start 5 - offset detection procedure stop and reading operation. the purpose of this test is to check if a d.c. offset (2v typ.) is present on the outputs, produced by input capacitor with anomalous leakage current or humidity between pins. the delay from 3 to 4 can be selected by software, starting from 1 ms start address byte with d0 = 0 ack ib1 ack ib2 ack stop xx00x000 0xx1xx10 start address byte with d0 = 0 ack ib1 ack ib2 ack stop xxxxxxxx xxx0xxx0 start address byte with d0 = 0 ack ib1 ack ib2 ack stop xx1xx11x xxx1xxx0 start address byte with d0 = 1 ack db1 stop
low voltage "start-stop" operation tda7565 16/19 doc id 9800 rev 4 6 low voltage "start-stop" operation the most recent oem specification are requiring automatic stop of car engine at traffic lights in order to reduce emissions of polluting substances. the tda7565, thanks to its integrated switching voltage converter, allows a continuous operation when battery falls down to 6/7 v during such conditions, withou t producing pop noise. the maximum system power will be reduced accordingly. the internal converter must be enabled and programmed in order to supply 15 v (d3 (ib2) = 0; d6 (ib2) = 0) . the suggested voltage frequency switching is 150 khz (d6 (ib1) = 1; d7 (ib1) = 0) . the following curve is a worst case condition for a start-stop system. the tda7565, with the switching converter powered on, can sustain this cranking curve without any audio signal interruption. figure 7. worst case condition for a start-stop system diagram v b1 = 12 v, v b2 = 6 v, v b3 = 7 v r i 0.01 (internal resistor of power supply) recovery time from test start to tr is 1 s t r = 2 ms t 1 = 1 ms (the shortest time, at cranking simulation power supply, is 5 ms) t 2 = 15 ms t 3 = 1 s t f = 0.5 s v b1 v v b3 v b2 t f t 3 t 2 t 1 t r t
tda7565 package information doc id 9800 rev 4 17/19 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 8. flexiwatt27 (vertical) mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 4.45 4.50 4.65 0.175 0.177 0.183 b 1.80 1.90 2.00 0.070 0.074 0.079 c 1.40 0.055 d 0.75 0.90 1.05 0.029 0.035 0.041 e 0.37 0.39 0.42 0.014 0.015 0.016 f (1) 0.57 0.022 g 0.80 1.00 1.20 0.031 0.040 0.047 g1 25.75 26.00 26.25 1.014 1.023 1.033 h (2) 28.90 29.23 29.30 1.139 1.150 1.153 h1 17.00 0.669 h2 12.80 0.503 h3 0.80 0.031 l (2) 22.07 22.47 22.87 0.869 0.884 0.904 l1 18.57 18.97 19.37 0.731 0.747 0.762 l2 (2) 15.50 15.70 15.90 0.610 0.618 0.626 l3 7.70 7.85 7.95 0.303 0.309 0.313 l4 5 0.197 l5 3.5 0.138 m 3.70 4.00 4.30 0.145 0.157 0.169 m1 3.60 4.00 4.40 0.142 0.157 0.173 n 2.20 0.086 o 2 0.079 r 1.70 0.067 r1 0.5 0.02 r2 0.3 0.12 r3 1.25 0.049 r4 0.50 0.019 v5? (typ.) v1 3? (typ.) v2 20? (typ.) v3 45? (typ.) (1): dam-bar protusion not included (2): molding protusion included flexiwatt27 (vertical) h3 r4 g v v g1 l2 h1 h f m1 l flex27me v3 o l3 l4 h2 r3 n v2 r r2 r2 c b l1 m r1 l5 r1 r1 e d a v1 v1 7139011 pin 1
revision history tda7565 18/19 doc id 9800 rev 4 8 revision history table 12. document revision history date revision changes 20-sep-2003 1 initial release. 1-jul-2008 2 document reformatted. document status prom oted from product preview to datasheet. 25-jan-2010 3 updated features and description on page 1 . updated table 4: electrical characteristics . added section 6: low voltage "start-stop" operation . 03-feb-2010 4 minor text changes.
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